From a23e928a1f4424d3e7c6a1fdb4883f5dbd46fba2 Mon Sep 17 00:00:00 2001
From: Bent Bisballe Nyeng <deva@aasimon.org>
Date: Tue, 23 Jan 2018 20:53:40 +0100
Subject: Add vhd2vl VHDL to Verilog conversion tool.

---
 fpga-toolchain/build.sh | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/fpga-toolchain/build.sh b/fpga-toolchain/build.sh
index 57d06fe..e052da0 100755
--- a/fpga-toolchain/build.sh
+++ b/fpga-toolchain/build.sh
@@ -66,4 +66,18 @@ then
 		popd
 fi
 
+# Couldn't get it to compile...
+#D=yodl
+#SRC=https://github.com/forflo/yodl.git
+
+D="vhd2vl"
+if [ ! -d $D ]
+then
+                git clone https://github.com/ldoolitt/vhd2vl.git $D
+                pushd $D/src
+		make
+                cp vhd2vl $ROOT/install/bin
+                popd
+fi
+
 popd
-- 
cgit v1.2.3