diff options
Diffstat (limited to 'fpga-toolchain/experiments')
-rw-r--r-- | fpga-toolchain/experiments/top.v | 100 |
1 files changed, 60 insertions, 40 deletions
diff --git a/fpga-toolchain/experiments/top.v b/fpga-toolchain/experiments/top.v index 421c0a4..6a6e3ad 100644 --- a/fpga-toolchain/experiments/top.v +++ b/fpga-toolchain/experiments/top.v @@ -1,42 +1,62 @@ -// Blink an LED provided an input clock -/* module */ -module top (hwclk, mosi, led1, led2, led3, led4, led5, led6, led7, led8, clkout , out); - /* I/O */ - input hwclk; - input mosi; - output led1; - output led2; - output led3; - output led4; - output led5; - output led6; - output led7; - output led8; - output clkout; - output out; - wire clkout; - - /* Counter register */ - reg [31:0] counter = 32'b0; - reg [8:0] shiftreg = 9'b1; - - /* LED drivers */ - assign led1 = shiftreg[0]; - assign led2 = shiftreg[1]; - assign led3 = shiftreg[2]; - assign led4 = shiftreg[3]; - assign led5 = shiftreg[4]; - assign led6 = shiftreg[5]; - assign led7 = shiftreg[6]; - assign led8 = shiftreg[7]; - - assign clkout = hwclk; - assign out = shiftreg[8]; - - /* always */ - always @ (negedge hwclk) - begin - shiftreg = (shiftreg << 1) + mosi; - end +// File blinky.vhdl translated with vhd2vl v3.0 VHDL to Verilog RTL translator +// vhd2vl settings: +// * Verilog Module Declaration Style: 2001 + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications (C) 2010 Shankar Giri +// Modifications Copyright (C) 2002-2017 Larry Doolittle +// http://doolittle.icarus.com/~larry/vhd2vl/ +// Modifications (C) 2017 Rodrigo A. Melo +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module top( +input wire hwclk, +input wire mosi, +output wire led1, +output wire led2, +output wire led3, +output wire led4, +output wire led5, +output wire led6, +output wire led7, +output wire led8, +output reg outnext +); + + + + +reg [7:0] shift_reg; + + assign led1 = shift_reg[0]; + assign led2 = shift_reg[1]; + assign led3 = shift_reg[2]; + assign led4 = shift_reg[3]; + assign led5 = shift_reg[4]; + assign led6 = shift_reg[5]; + assign led7 = shift_reg[6]; + assign led8 = shift_reg[7]; + assign outclk = hwclk; + always @(posedge hwclk) begin + shift_reg[7:0] <= {shift_reg[6:0],mosi}; + end + + always @(negedge hwclk) begin + outnext <= shift_reg[7]; + end + endmodule |