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// File blinky.vhdl translated with vhd2vl v3.0 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002-2017 Larry Doolittle
// http://doolittle.icarus.com/~larry/vhd2vl/
// Modifications (C) 2017 Rodrigo A. Melo
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module top(
input wire hwclk,
input wire mosi,
output wire led1,
output wire led2,
output wire led3,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
output wire led8,
output reg outnext
);
reg [7:0] shift_reg;
assign led1 = shift_reg[0];
assign led2 = shift_reg[1];
assign led3 = shift_reg[2];
assign led4 = shift_reg[3];
assign led5 = shift_reg[4];
assign led6 = shift_reg[5];
assign led7 = shift_reg[6];
assign led8 = shift_reg[7];
assign outclk = hwclk;
always @(posedge hwclk) begin
shift_reg[7:0] <= {shift_reg[6:0],mosi};
end
always @(negedge hwclk) begin
outnext <= shift_reg[7];
end
endmodule
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